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Published: May 2, 2007 | Source: DailyTech | Author: Matthew Fogg

ClearSpeed Announces Math Processor

ClearSpeed Announces Math Processor

ClearSpeed e620

ClearSpeed Technology , the world leader in acceleration technology for high performance computing (HPC) applications yesterday released its new e620 Maths Processor.

ClearSpeed’s CSX600 is an embedded low power data parallel coprocessor. It provides 25 GFLOPS of sustained single or double precision floating point performance, while dissipating an average of 10 Watts. Using 64-bit addressing, each CSX600 can support multi-gigabyte DDR2 SDRAMs via a local ECC protected memory interface. The CSX600 processor is actually a system-on-a-chip (SoC), based around the combination of ClearSpeed’s patented multi-threaded array processor (MTAP) and ClearConnectâ„¢ Network on Chip (NoC) technology. The MTAP architecture has been designed to provide unparalleled performance-per-watt, while the low-power ClearConnect NoC provides straightforward system-wide concurrent bandwidth.

According to our source, AMD were looking to revive the maths co-processor technology for its Opteron processors around a year ago. And it appears that ClearSpeed are looking to create a socket plugin for AMD’s up and coming ‘Torrenza’ accelerated computing platform. With a reported 20 times increase in performance over conventional servers, the corporate world would be mad not to utilise the technology. Below are some of the performance and feature specs of the e620 (taken from ClearSpeed’s website)

Performance

  • 10W average power dissipation
  • 25 GFLOPS sustained double precision DGEMM
  • 96 Gbytes/s internal memory
  • 3.2 Gbytes/s external memory
  • 2 x 3.2 Gbytes/s chip-to-chip bandwidth

Features

  • 96 high-performance processing elements cores, each with dedicated memory
  • 6 Kbytes high bandwidth memory per processing element
  • 128 Kbytes on-chip scratchpad memory
  • 64-bit DDR2 DRAM interface with ECC support
  • ClearConnect provides on-chip and inter-chip data network
  • Host interface and debug port
  • 64-bit virtual, 48-bit physical addressing
  • On-chip instruction and data caches
  • On-chip DMA controller

ClearSpeed CSX600

architecture

Want more information on ClearSpeed’s e620 Maths Processor? Then head to their website here

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