Twice the Performance and Backward CompatibleFollowing a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, the data shows that 8GT/s can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full mechanical compatibility and with negligible impact to the PCIe protocol stack. The 8GT/s bit rate represents a doubling of the delivered bandwidth by removing the requirement for the 8b/10b encoding scheme supported in prior versions of PCIe architecture, which imposed a 20 percent overhead on the raw bit rate. The PCIe 3.0 specification will introduce a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies. The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond.
“Experts in the PCIe Electrical Workgroup analyzed both 10GT/s and 8GT/s as target bit rates for the next generation of PCIe architecture, and after careful consideration of several factors, including power, implementation complexity and silicon area, recommended 8GT/s,” said Al Yanes, PCI-SIG chairman. “This allows us to satisfy the next generation performance requirements for all existing PCIe applications while maintaining backward compatibility, and at the same time broadening the adoption of this pervasive technology into new and emerging applications and usage models.”
PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG. The PCI-SIG compliance tools are also calibrated with these findings to ensure maximum interoperability and robustness of products developed to these specifications. When complete, the PCIe 3.0 Base specification will consolidate all existing and future protocol extensions, and will be available for PCI-SIG member reviews through all phases of the PCI-SIG specification development process. These protocol extensions, which are being defined by the PCI-SIG to expand the usage model and adoption of PCI Express architecture in new and emerging applications, are intended to optimize interconnect latency and platform resource efficiency by introducing new specifications for data reuse, dynamic power management, and related optimizations in the I/O hierarchy.
2007 Marks PCIe TransitionIn addition to announcing the bit rate for PCIe 3.0, 2007 will mark another important milestone for the PCI-SIG: the transition from PCIe 1.x to PCIe 2.0. With the recent availability of PCIe 2.0 compliance tests and tools, PCI-SIG is continuing its campaign to provide technical education and compliance workshops both in the U.S. and abroad. It is anticipated that by the end of this year, the first wave of PCIe 2.0 products will be broadly available in the market.