PCI-SIC accelerates the creation of PCIe 5.0
PCI-SIC accelerates the creation of PCIe 5.0
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At the PCI-SIG Developers Conference, the organisation announced that they were accelerating the development of PCIe 5.0, which is designed to offer 128GB/s of total bandwidth, 4x that of PCIe 3.0 when both are using x16 links.Â
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Right now, PCI-SIG expects to complete their PCIe 5.0 standard sometime in 2019, with the organisation already releasing version 0.3 of the standard to their members. Â
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PCIe 5.0 will enable users to get more bandwidth out of fewer PCIe lanes and enable the creation of faster PCIe devices, allowing 400Gb/s Ethernet solutions to be created for servers or to reduce the PCIe requirements of modern M.2, U.2 or PCIe storage devices.Â
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PCI-SIG are designing this standard not to meet modern industry standards but to exceed them, making PCIe 5.0 even faster than Nvidia’s own NVLink 2.0 interconnects. Â
ÂIn our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O,“PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs.
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 (PCIe 5.0 x4 is as fast as PCIe 3.0 x16)
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Moving forward the speed of PCIe lanes will be in great demand, as PCIe storage devices become more common and both NAND and other non-volatile memory standards like XPoint become more common.Â
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You can join the discussion on PCIe 5.0 on the OC3D Forums.Â
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