Samsung has started producing 3nm silicon with their innovative Gate-All-Around (GAA) transistors
Will Samsung's Gate-All-Around (GAA) transistors push them ahead of TSMC?
Published: 30th June 2022 | Source: Samsung |
Samsung claims up to 23% performance improvements with their new 3nm GAA transistors
Within the silicon market, relatively few manufacturers produce their own chips in-house. Most companies design their own products and hire dedicated silicon foundries to produce their chips for them. This cuts down on R&D costs, and ensures access the latest an greatest silicon manufacturing technologies.
The leading edge silicon foundry market is dominated by two major players, Samsung and TSMC, both of which are in a constant battle to become the semiconductor market's leading manufacturer. In recent years, TSMC has been ahead of Samsung, but that could soon change with the introduction of 3nm lithography nodes.
Samsung has started producing silicon using their 3nm Gate-All-Round (GAA) transistor architecture. GAA transistors are a post-FinFET transistor design that offers improved performance characteristics. Samsung's version of GAA transistors is called Multi-Bridge-Channel FET (MBCFET), which improves upon the standard GAA concept with wider channel widths with nanosheets.
The name GAA (Gate-All-Round) describes everything that you need to know about the technology. It overcomes the scaling and performance limitations of FinFET transistors by featuring four gates around all sides of a channel to offer full coverage. By comparison, FinFET effectively covers three sides of a fin-shaped (hence FinFET) channel. In effect, GAAFET takes the idea of a three-dimensional transistors to the next level.
With their first generation 3nm MBCFET transistors, Samsung claims that they can deliver up to 45% efficiency gains over their 5nm node, up to 23% performance gains, and up to a 16% area reduction. With their second generation 3nm process, Samsung plans to deliver power consumption reductions of up to 50%, performance gains of up to 30%, and area reductions of up to 35% when compared to 5nm.
With their latest lithography node, Samsung can allow manufacturers to create more power efficient, more performant, and more transistor dense chips. If these claims are true, Samsung should be able to gain a lot of ground against TSMC, potentially winning over some high profile customers in the process.
Below is Samsung's Press Release about their new 3nm GAA transistors, which are now being used to produce chips at Samsung's foundries.
Press Release - Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture
Samsung Electronics, the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture. Multi-Bridge-Channel FET (MBCFET ), Samsung's GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability. Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors.
"Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry's first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world's first 3 nm process with the MBCFET," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology."
Design-Technology Optimization for Maximized PPA
Samsung's proprietary technology utilizes nanosheets with wider channels, which allow higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. Utilizing the 3 nm GAA technology, Samsung will be able to adjust the channel width of the nanosheet in order to optimize power usage and performance to meet various customer needs.
In addition, the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO), which helps boost Power, Performance, Area (PPA) benefits. Compared to 5 nm process, the first-generation 3 nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5 nm, while the second-generation 3 nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.
Providing 3 nm Design Infrastructure & Services With SAFE Partners
As technology nodes get smaller and chip performance needs grow greater, IC designers face challenges of handling tremendous amounts of data to verify complex products with more functions and tighter scaling. To meet such demands, Samsung strives to provide a more stable design environment to help reduce the time required for design, verification and sign-off process, while also boosting product reliability.
Since the third quarter of 2021, Samsung Electronics has been providing proven design infrastructure through extensive preparation with Samsung Advanced Foundry Ecosystem (SAFE ) partners including Ansys, Cadence, Siemens and Synopsys, to help customers perfect their product in a reduced period of time.
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