AMD and Intel confirm “ACE” AI Compute Extensions for x86
New x86 ACE extensions are coming, aiming to boost CPU-based AI/ML performance
The x86 Ecosystem Advisory Group, which was formed by AMD and Intel in 2024, has unveiled new AI Compute Extensions “ACE” for future x86 CPUs. This is a standardised set of instructions that aims to accelerate AI and ML workloads. Specifically, these features focus on matrix multiplication and reduced-precision data formats, which are common in the AI space.
AMD and Intel have released their new ACE specifications through the x86 Ecosystem Advisory Group, with both brands committing to supporting the standard with future CPUs. This standardisation prevents excessive fragmentation within the x86 CPU market, avoiding the problems that faced the AVX-512 instruction set and its variations.
ACE extensions aim to accelerate matrix multiplication and improve efficiency for these workloads on x86 processors. These accelerators may become incredibly important for future AI workloads. Their utility outside of these workloads is unknown.
AI Compute Extensions (ACE) Specification
x86 extensions for accelerating computation tasks, initially focusing on matrix multiplication kernels and reduced precision data formats important to ML workloads.
The ACE extensions define matrix multiplication primitives that augment AVX and scalar code with new capabilities, adding:
- ACE register state, including tile and block scale registers
- Data processing operations that consume AVX register input and operate on tile register state
- Data move operations to move data between ACE register state and AVX registers
- State and operations for system management
ACE provides tight integration between AVX vectors and ACE tile registers, combining high compute density tile processing operations with the comprehensive data processing features of AVX.
In addition to matrix acceleration, a number of dedicated format convert operations are provided under the AVX10 framework.
AMD ACE support
With its CPU roadmap, AMD has promised “new AI Data Type Support” and “more AI pipelines” with its Zen 6 CPUs. Furthermore, AMD has promised a “new Matrix Engine” and “AI Data Format Expansion” with Zen 7. This likely means that ACE support will arrive with AMD’s Zen 7 CPUs and its “new Matrix Engine”, though this remains unconfirmed.
The beauty of the x86 Ecosystem Advisory Group is this. Their instructions will have support from both AMD and Intel, giving software developers a strong incentive to use them. These aren’t instructions that are specific to certain CPUs from a single vendor. Furthermore, CPU makers are also unlikely to abandon these instructions with future product generations. If these new instructions can accelerate workloads, software vendors have no reason not to support them.
Current ACE instruction documentation mentions support for the following data formats.
| Format | Description | Notes |
|---|---|---|
| INT8 | 8-bit integer | |
| INT32 | 32-bit integer | |
| FP32 | SE8M23 | As defined by IEEE-754 |
| BF16 | SE8M7 | |
| FP16 | SE5M10 | |
| E8M0 | 8-bit unsigned exponent | Used for power-of-two block scale formats |
| FP8 | 8-bit floating point | Defined in OCP 8-bit Floating Point Specification (OFP8) [1]. Also refer to OCP Microscaling Formats (MX) Specification [2]. |
| MX FP8 | 8-bit floating point formats (SE5M2, SE4M3) | |
| MX FP6 | 6-bit floating point formats (SE3M2, SE2M3) | |
| MX FP4 | 4-bit floating point format (SE2M1) | |
| MX INT8 | 8-bit fixed-point fractional format |
You can join the discussion on AMD/Intel’s ACE specification on the OC3D Forums.
