AMD's Milan-X Processors Specs have Leaked, revealing SKUs with 768MB of L3 Cache
Soon, AMD's server CPUs may have over a gigabyte of L3 cache
Published: 16th September 2021 | Source: @ExecuFix |
AMD's Milan-X CPUs are cache crazy
AMD's 3D V-Cache technology will allow them to create insane processors with ludicrous amounts of L3 cache. Back at Computex 2021, AMD showcased a V-Cache enhanced Ryzen 5900 processor with 192MB of L3 cache, 3x as much cache as a standard Ryzen 9 5900X.
The latest CPU specifications leaks from EcecutableFix (@ExecuFix) have showcased what AMD's V-Cache technology will do to the company's Milan series of EPYC processors. To make a long story short, AMD's Milan-X CPUs will deliver an insane amount of L3 Cache to its future EPYC users.
AMD's Milan-X EPYC 7773X will reportedly offer users 64 cores and 128 threads with a 2.2GHz base clock speed with a 3.5GHz boost clock. This CPU allegedly offers users 768MB of L3 cache, three times as much L3 cache as AMD's EPYC 7763.
To get this much L3 cache, every CPU chiplet on AMD's EPYC 7773X processor will utilise AMD's V-Cache technology. Standard Zen 3 Ryzen/EPYC 8-core chiplets feature 32MB of L3 cache, while AMD's V-Cache chiplets will offer chiplets an additional 64MB of L3 cache. Together, this gives each Zen 3 chiplet 96MB of total L3 cache, which across eight chiplets gives Milan-X a maximum L3 cache size of 768MB.
ExecuFix has also reported that AMD's 32-core 7573X, 24-core 7473X, and 16-core 7373X will also feature 768MB of total L3 cache. Remember when full PCs featured less than 768MB of total memory? Soon, it looks like AMD will be offering customers almost a Gigabyte of cache!
AMD's V-Cache technology does two things, it increases L3 cache capacity, allowing more data to be stored on-chip, and it significantly increases AMD's L3 cache bandwidth. Both of these changes will impact Milan X's performance. By keeping more data on-chip, Milan X processors will not need to access DRAM as frequently, freeing up that bandwidth for other tasks while granting users faster access to on-chip data.
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