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Published: November 12, 2018 | Source: AMD | Author: Mark Campbell

AMD’s “Zen 2” IPC is 29.4% higher than Zen 1 in DKERN +RSA

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AMD’s “Zen 2” IPC is 29.4% higher than Zen 1 in DKERN +RSA

During AMD’s Next Horizon presentation, the company revealed their Zen 2 x86 architecture alongside their next-generation of EPYC processors, boasting an innovative “Chiplet” design while utilising TSMC’s 7nm process node for their CPU cores and a 14nm die for I/O interactions. 

Within the footnotes of AMD’s press release lies an exciting tidbit of information, detailing how AMD’s performance per clock, or rather Instruction Per Cycle (IPC), has increased over their 1st generation Zen processors, giving us our first glance at Zen 2’s throughput. 

In DKERN +RSA AMD’s Zen 2 architecture offered a staggering 4.53 IPC score, while their “Zen 1” generation CPU achieved 3.5 IPC, giving Zen 2 a boost of 29.4%. Some websites have been fixated on this 29.4% number, forgetting its context, but let’s have a better discussion as to this data’s relevance. 

As AMD’s footnotes confirm, this data refers to IPC (Instructions Per Cycle), which means that clock speeds should not play a major role here, making this 29% boost down to pure architectural advancement, not an increase in clock speed alone. It is also worth noting that this benchmarking data includes both floating point and integer benchmarks, which is another factor that is worth considering. 

One of AMD’s Zen 2 announcements was their increased floating point performance, revealing a tremendous 2x performance boost over Zen thanks to their 256-bit AVX calculation support, a change that will no doubt inflate the numbers of AMD’s previously mentioned benchmarks. This means that we should expect much lower gains in Integer benchmarks, with the most significant improvements coming in floating point calculations. At this time we do not know how much of AMD’s DKERN +RSA tests rely on floating point calculations and how much relies on Integer math, making it difficult to predict how much Zen 2’s Integer performance has improved over Zen 1.
   

    Estimated increase in instructions per cycle (IPC) is based on AMD internal testing for “Zen 2” across microbenchmarks, measured at 4.53 IPC for DKERN +RSA compared to prior “Zen 1” generation CPU (measured at 3.5 IPC for DKERN + RSA) using combined floating point and integer benchmarks.

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On the core side, Zen 2 offers a redesigned execution pipeline, featuring an improved branch predictor, a re-optimised instruction cache, better instruction pre-fetch and a larger Ops Cache, all of which will help increase Zen 2’s IPC (performance per clock) in a variety of workloads. Early leaks have suggested that AMD’s Zen 2 architecture will offer a 13+% boost in performance over Zen 2 in standard non-AVX applications, though AMD has not confirmed this data. 

Like every architectural leap in processor design, performance boosting techniques are largely application dependent, with each design change delivering performance advances to specific aspects of a processor’s functionality, rather than offer a ?% gain in every application under the sun.

When combined with possible clock speed boosts, AMD’s Zen 2 processors could offer a significant leap over their Zen/Zen+ counterparts over a range of PC applications, though we will have to wait a while before we start seeing real-world performance numbers from AMD’s next-generation CPU designs. 

You can join the discussion on the IPC improvements of AMD’s Zen 2 architecture on the OC3D Forums.  

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