Intel issues 10nm updates and reveals the industry’s first shipping 64-layer TLC 3D-NAND

Intel issues 10nm updates and reveals the industry's first shipping 64-layer TLC 3D-NAND

Intel issues 10nm updates and reveals their first shipping 64-layer TLC 3D-NAND

 
At their Beijing Technology and Manufacturing day, Intel has delivered an update on their 10nm products and the company’s 3D NAND production, revealing that they are they are currently shipping the world’s first 64-layer TLC 3D NAND for datacenter applications. 
Intel has also reiterated their claims that their 10nm process is a full generation ahead of their competitors, with “10nm” offerings from Samsung and TSMC offering less transistor density. This means that Intel’s 10nm is expected to produce chips with a lower cost per transistor and offer more transistors per unit of die area.  
 
Below is a comment from Intel’s group president of Manufacturing, Operations and Sales, Stacy Smith;  

  

Intel manufacturing processes advance according to Moore’s Law, delivering ever more functionality and performance, improved energy efficiency and lower cost-per-transistor with each generation,

We are pleased to share in China for the first time important milestones in our process technology roadmap that demonstrate the continued benefits of driving down the Moore’s Law curve.

 

Intel states that their 10nm FinFET node offers 2.7x the transistor density of their 14nm production node, which will allow Intel to push more transistors into their 10nm products at lower die sizes. 

This is a huge jump for Intel, allowing them to deliver CPU cores with higher transistor counts, perhaps to increase per core performance or add additional features or allow for more cores to be fitted onto smaller package/die sizes.

At this event, Intel showcased a 10nm Cannon Lake CPU wafer for the first time, though sadly Intel did not release any images of the wafer to the public.   

Intel issues 10nm updates and reveals the industry's first shipping 64-layer TLC 3D-NAND

 

At this event, Intel also reiterated that the foundry industry required a standardized unit of measurement for process node sizes, as today node size is more of a marketing term than an objective measurement.

Intel wants the industry to move to a model where nodes are named using a standardised measure of transistor density, though it is unlikely that other manufacturers will agree to this given Intel’s claimed leadership in this regard. 

An update was also delivered on Intel’s collaboration with ARM to accelerate the production of ARM SoCs on Intel’s 10nm process. Intel has been able to display a test wafer chip for an ARM Cortex-X75, which was able to run at speeds in excess of 3.0GHz, which is pretty fast for an ARM CPU. 

Intel issues 10nm updates and reveals the industry's first shipping 64-layer TLC 3D-NAND  

Right now it is expected that Intel will be releasing 10nm consumer products by mid-2018, though it is expected that these products will hit the mobile markets first given the node’s power consumption and size characteristics, both of which are best suited to the mobile/notebook market. 

 

You can join the discussion on Intel’s 10nm manufacturing process on the OC3D Forums.