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Intel announces their new Mesh Interconnect for their Skylake-X Xeon processors

Intel announces their new Mesh Interconnect for their Skylake-X Xeon processors

Intel announces their new Mesh Interconnect for their Skylake-X Xeon processors

Intel announces their new Mesh Interconnect for their Skylake-X Xeon processors

 
When scaling to increasingly high core counts, inter-core communication can become a huge problem, whether it be the speed of the latency of communicated data. These factors can have a huge effect on performance and now Intel has reached the limitations of their "Ring-Bus" technology, which was first introduced in 2008. 
 
In an ideal world, every CPU core would have a direct connection to every other CPU core, allowing them to transfer data when required as quickly as possible and with minimal latency. As CPU core counts rise, the viability of a core-core interconnect between every CPU core becomes an impossible task, as the number of interconnects become to many and too complex for affordable/manufacturable designs.  
 
This is what the Rings bus was designed for, taking data on what can be described as a conveyor belt that transfers data around the CPU in a loop to the desired core. While this solution was innovative back in 2008, core counts have done nothing but increase since then, so much so that large ring buses could suffer from latency spikes when one core is communicating with the farthest away core.
 
With modern high-core count Xeons problems only get worse, as they are so large that two Ring Buses need to be used, requiring the use of Intel's QPI interconnect that goes between the two buses. This adds additional latency and complexity into the mix, forcing Intel to rethink their core-core interconnect design. 
 
This is where Intel's new Mesh Interconnect comes into play, 

  

Intel announces their new Mesh Interconnect for their Skylake-X Xeon processors

 

In effect, INtel's new Mesh design replaces the "Ring Bus" data transports with an "XY" style transport system, offering more direct core-core connection and minimising the minimum amount of time it takes for data to reach other CPU cores. 

Instead of running around the Ring Bus to deliver data to other CPU cores, Mesh allows data to take a more direct approach to other cores, minimising latency while also offering higher data transport speeds, while also eliminating the "dual ring bus" problem from HCC (High Core Count) CPU designs. 

  
Intel announces their new Mesh Interconnect for their Skylake-X Xeon processors

 

Intel's new Mesh transport design sounds very similar to AMD's new Infinity Fabric design, though it is worth noting that AMD's Infinity Fabric is a much broader technology that can be applied to CPUs, GPUs and APUs. 

This new interconnect will allow Intel to increase the multi-threaded performance of their new high core count CPUs, though at this time it is unknown how much of an impact this will have on Skylake-X's overall performance. 

 

You can join the discussion on Intel's new Mesh Core Interconnect on Skylake-X on the OC3D Forums

 

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Most Recent Comments

16-06-2017, 11:08:15

TheF34RChannel
Aw beat me to it. Stupid work getting in the way of fun!Quote

16-06-2017, 11:18:57

Bartacus
They should call it infinity mesh. Quote
Reply
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