TSMC’s 5nm node is set to enter risk production in H2 2019

While Intel’s 10nm issues are ongoing, TSMC has continued to march forward towards smaller nodes, confirming their plans to start 5nm risk production in the second half of 2019.  

On top of that, TSMC expects their new 7nm node to account for 20% of their total revenue on 2019, showcasing the huge demand for a leading edge process node, with TSMC gobbling up the business that would have gone to competing 7nm nodes from the likes of GlobalFoundries, who recently exited the leading edge foundry game. 

Before 5nm, TSMC plans to develop a 7nm FinFET Plus node, which adopts EUV technology for several layers of the manufacturing process, with 5nm FinFET further utilising the technology for more critical layers, further reducing the need for multi-patterning. This change will also allow 5nm to offer a significant amount of transistor scaling when compared to 7nm, with early reports estimating an area reduction of 45% when compared to 7nm FinFET. 

For context, TSMC’s 7nm FinFET node already offers a 70% area reduction over 16nm FinFET, making 5nm an extremely compact node, though the power savings and performance boosts provided by 5nm are expected to be smaller.