PCI-SIG has finally launched the PCI Express 5.0 Standard
Double the bandwidth of PCI 4.0 with full backwards compatibility
Published: 29th May 2019 | Source: PCI-SIG |
PCI-SIG has finally launched the PCI Express 5.0 Standard
PCI Express 5.0 comes just 18 months after the release of the PCI Express 4.0 standard, with the standard's launch coming shortly after the reveal of several PCI Express 4.0 compliant products. With this new iteration, PCI Express can no offer a 4x bandwidth advantage per lane over today's PCI Express 3.0 products, delivering game-changing levels of bandwidth.
Below are a few highlights of the PCI Express 5.0 standard:
- Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration
- Leverages and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits
- Implements electrical changes to improve signal integrity and mechanical performance of connectors
- Includes new backwards compatible CEM connector targeted for add-in cards
- Maintains backwards compatibility with PCIe 4.0, 3.x, 2.x and 1.x
With this step forward, PCI-SIG has enabled devices on par with Samsung's 970 Pro series of SSDs to operate on a single PCIe 5.0 lane, rather than four PCIe 3.0 lanes, enabling devices which are up to four times as fast, or enable users to utilise up to four times as many equivalent devices. Not bad for two years of work.
It is worth noting that it will take some time before PCIe 5.0 becomes available on mainstream hardware. PCI-SIG released the PCIe 4.0 standard in October 2017, and AMD will be the first manufacturer to offer PCI Express 4.0 support on mainstream hardware, with plans to launch their PCI Express 4.0 compatible X570 motherboard platform in July 2019. With this in mind, we shouldn't expect PCIe 5.0 to be available on mainstream hardware platforms until at least 2021.
You can join the discussion on PCI-SIG releasing their PCI Express 5.0 standard on the OC3D Forums.
Most Recent Comments
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Originally Posted by NeverBackDown
Can basically run 4 2080tis off one x16 slot and still be like oh that's it?
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Originally Posted by HJ1mech
What would this mean for egpu setups? Would 5.0 basically erase the fps penalty you have because TB3 is only 4 lanes?
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So if they used 2 lanes, it would be double the bandwidth, 3 lanes 3x the bandwidth, etc. Would it erase the penalty? 4.0 might be able to do that, the real issue then becomes latency which neither will solve. Though it isn't all that bad as it is.
I'd expect to see PCIe4.0 implementations first although it shouldn't be around all that long.Quote
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