PCI-SIG plans to update us on PCIe 6.0 this week
PCIe 6.0, because who doesn't want more bandwidth?
Published: 1st June 2020 | Source: PCI-SIG |
PCI-SIG plans to update us on PCIe 6.0 this week
Even now, PCIe 4.0 is in its infancy, but that will start to change with the release of AMD's low-cost B550 chipset, and while PCIe 5.0 is ready to be adopted by chipmakers, PCI-SIG believes that the march of progress shouldn't stop there. PCI-SIG wishes to remain the king of PC interconnects, and that means that they need to continue to evolve while maintaining backwards compatibility.
This week, PCI-SIG plans to deliver the press and update on PCIe 6.0, an update which will likely reveal a new pre-release version of the PCIe 6.0 standard. While the ratification of PCIe 6.0 is due to occur in 2021, these early standard interactions will allow manufacturers to start tinkering with the high-bandwidth interconnect.
PCIe 6.0 will be the new hotness when it comes to PC interconnectivity, packing a 2x increase in transfer speeds over PCIe 5.0, a 4x boost in raw bit rate over PCIe 4.0 and a whopping 8x improvement over what PCIe 3.0 configuration can deliver. For context, that allows a single PCIe 6.0 lane to offer users as much bandwidth as a PCIe 3.0 8x lane configuration, which is more than enough bandwidth for most of today's graphics cards.
Right now, PCIe 6.0 is a standard is in its planning stages, with PCI-SIG planning to ratify and release their full standard in 2021, two years after the release of PCIe 5.0. In the PC space, it typically takes two-three years for PCIe standards to make it into the PC market, making it probable that we will start seeing PCIe 6.0 compliant PCs in 2023 or 2024.
Below is a brief overview of the PCIe 6.0 standard, in its current form.
PCIe 6.0 Specification Features
- Delivers 64 GT/s raw bit rate and up to 256 GB/s via x16 configuration
- Utilises PAM-4 (Pulse Amplitude Modulation with four levels) encoding and leverages existing 56G PAM-4 in the industry
- Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
- Maintains backwards compatibility with all previous generations of PCIe technology
To put the performance of PCIe 6.0 into context, it could enable M.2 devices to deliver speeds that are up to eight times faster than today's Samsung 970 Pro series SSD, which is widely regarded as one of the best performing PCIe 3.0 M.2 SSDs on the market. Another way to put it is with PCIe 6.0, the performance of a PCIe 3.0 16x configuration is equivalent to two PCIe 6.0 lanes.
PCIe 6.0 will enable higher levels of bandwidth for those who need it while granting PC users access to today's bandwidth levels over fewer PCIe lanes. The only problem with this rapid evolution is that new PCIe 4.0 devices will soon find themselves replaced with PCIe 5.0 and then PCIe 6.0 over the next 5 or so years. That said, should e complain about technology progressing too quickly?
You can join the discussion on PCI-SIG's upcoming PCIe 6.0 standard on the OC3D Forums.
Most Recent Comments
As you said we won't see this for a while but I'm sure HPC/Datacenter markets are itching for something like this.
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Now PCI-SIG are moving as fast as they can to prevent themselves from becoming obsolete. Bandwidth is a big deal in the HPC market, be it in supercomputers, datacenters or in the world of AI compute. TBH, I wouldn't be surprised if PCIe 7.0 wasn't revealed (as in being worked on) before 2023.Quote
Bandwidth is a big deal for this market. There's a reason why Nvidia created NVLink and AMD created Infinity Fabric Link for their datacenter GPUs. PCI was stagnant for too long after PCIe 3.0 released.
Now PCI-SIG are moving as fast as they can to prevent themselves from becoming obsolete. Bandwidth is a big deal in the HPC market, be it in supercomputers, datacenters or in the world of AI compute. TBH, I wouldn't be surprised if PCIe 7.0 wasn't revealed (as in being worked on) before 2023. |
Also InfinityFabric has extra controll lanes called Scalable Control Fabric which is in charge of monitoring and controlling different dies thermals , clock , power and many other low level aspects of a single die.
So as they are similar IF and PCIe they are also and very different and can't fully overlap each other which means they can't be true competitors to each other.Quote