The PCIe 6.0 Specification has been Finalised, enabling a 4x bandwidth boost over PCIe 4.0
PCIe 6.0 is one of PCI-SIG's most significant upgrades to date
Published: 12th January 2022 | Source: PCI-SIG |
PCIe 6.0 is here, and it it can deliver speeds of 128GB/s over x16 slots
It's official, PCI-SIG has officially finalised their PCIe 6.0 specification, achieving double the bandwidth and power efficiency of PCIe 5.0 while promising users low latency throughput, backwards compatibility and reduced bandwidth overhead over prior versions of the standard.
PCIe 6.0 will offer users data transfer rates of up to 8GB/s per lane, which is 2x faster than PCIe 5.0, 4x faster than PCIe 4.0 and 8x faster than PCIe 3.0. For context, today's fastest PCIe 4.0 (x4) M.2 SSDs offer sequential read speeds of around 7 GB/s, speeds that can now be achieved by a single PCIe 6.0 lane.
The two major changes to the PCIe standard with PCIe 6.0 is its use of Pulse Amplitude Modulation with 4 levels (PAM4 Signalling) and Flow Control Unit (FLIT) encoding, which enable PCIe 6.0's bandwidth boost. New error correct and redundancy checks also enable PCIe 6.0 to offer users higher data rates without increased error rates or latency.
PCI-SIG's rapid advancement with PCIe has seen bandwidth increase by a factor of 8 over the past 5 years. PCIe 4.0 was finalised in June 2017, and now PCIe 6.0 has been finalised with a 4x increase in bandwidth. The move from PCIe 3.0 to PCIe 4.0 was slow, but PCI-SIG's innovations since then have been rapid, and it seems to be only a matter of time before work on PCIe 7.0 begins.
PCIe 6.0 Specification Features
- 64 GT/s raw data rate and up to 256 GB/s (128 GB/s bi-directional) via x16 configuration
- Pulse Amplitude Modulation with 4 levels (PAM4) signaling, levraging existing PAM4 already available in the industry
- Lightweight Forward Error Correct (FEC) and Cyclic Redundancy Check (CRC) mitigate the bit error rate increase associated with PAM4 signaling
- Flit (flow control unit) based encoding supports PAM4 modulation and works in conjunction with the FEC and CRC to enable double the bandwidth gain
- Updated Packet layout used in Flit Mode to provide additional functionality and simplify processing
- Maintains backwards compatibility with all previous generations of PCIe technology
PCIe 6.0 was designed to meet the needs of future devices within the PC and enterprise markets, with Machine Learning, Artificial Intelligence, cloud computing and data storage being primary concerns for the industry. With 800G Ethernet cards coming this year, and even faster standards being on the horizon, faster PCIe interconnects will become vital for the industry moving forward.
With PCIe 6.0, PCI-SIG wants to meet the performance needs of the industry while doing so at a low cost. The backwards compatibility of the standard will also be useful for many markets, as it allows some older hardware to be maintained within newer networks.
While PCIe 6.0 is now an official standard, it will take years for this standard to be supported by new devices. PCIe 5.0 only recently became possible on Intel 12th Generation Alder Lake systems, and AMD plans to launch their PCIe 5.0 compatible AM5 platform later this year. PCIe 6.0 support is years away on a device level, as only now can device makers start using PCI-SIG's standards to create compliant products.
To put the performance of PCIe 6.0 into context, it could enable M.2 devices to deliver speeds that are up to four times faster than today's Samsung 980 Pro series SSD. Another way to put it is with PCIe 6.0, the performance of a PCIe 3.0 16x configuration is equivalent to two PCIe 6.0 lanes.
PCIe 6.0 will enable higher levels of bandwidth for those who need it while granting PC users access to today's bandwidth levels over fewer PCIe lanes. The only problem with this rapid evolution is that new PCIe 4.0 devices will soon find themselves replaced with PCIe 5.0 and then PCIe 6.0 over the next 5 or so years. That said, should we complain about technology progressing too quickly?