AMD Zen 7 CPU Specifications Leak – Big changes are coming
AMD Zen 7 CPU architecture leak unveils BIG changes
It looks like AMD’s planned Zen 7 CPU architecture will bring major changes to both Ryzen and EPYC. While Zen 6 hasn’t launched yet, AMD is already deep into planning for Zen 7, signalling that it isn’t resting on its laurels in the CPU space.
According to Moore’s Law is Dead, citing industry sources, AMD is aiming for 15-25% IPC (Instructions Per Cycle) gains with Zen 7. That means more performance per clock cycle. Additionally, AMD plans to deliver new ISA improvements to accelerate AI and optimise interactions between its CPUs and AI accelerators. AMD has already revealed some of this with its Zen CPU roadmap, which confirmed that Zen 6 would feature a “New Matrix Engine” and “AI Data Format Expansion”.
8% of AMD’s alleged Zen 7 IPC gains will reportedly come from cache design changes alone. This makes sense given AMD’s plans to increase L2 cache size with Zen 7 and to have up to 64MB of L3 cache on its rumoured 16-core “Silverton” CPU chiplets.
Changes for AMD with Zen 7
We have already mentioned Zen 7’s rumoured AI acceleration. This feature will boost the performance of some workloads, but not generic desktop applications. AMD is reportedly building Zen 7 using TSMC’s A14 lithography node. This is TSMC’s next major node after 2nm. With Zen 7, AMD will continue using TSMC’s newest nodes. This will prevent competitors from using newer nodes to gain a performance or efficiency advantage.
With Zen 7, AMD is reportedly giving each standard CPU core 2MB of L2 cache. This is a 2x increase over the L2 cache size of Zen 4 and Zen 5. L2 cache is much faster than L3 cache. As such, having more data in this lower-level cache will accelerate some workloads. Note that Intel’s move from Alder Lake to Raptor Lake included an L2 cache increase from 1.25MB to 2MB on Intel’s P-Cores, and that resulted in notable performance gains in games and other applications.
(Leaked information from Moore’s Law is Dead)
Up to 32 cores with Zen 6 Ryzen, but AMD could do better, at least theoretically
AMD has two core chiplet designs for Zen 7 Ryzen CPUs. These are their 16-core “Silverton” CCD and their 8-core “Silverking” CCD. Both designs feature 2MB of L2 Cache per core and 4MB of L3 cache per core. This gives the 8-core CCD 32MB of L3 Cache, and the 16-core CCD 64MB of L3 cache. Note that only AMD’s 16-core CCD will support L3 V-Cache/X3D upgrades.
With 16-cores per CCD and 64MB of unified L3 cache, AMD has doubled its CCD size from Zen 5 (8-cores with 32MB of L3 Cache). This means that each core has direct access to twice as much L3 cache. It also means that 16 cores can interact without transferring data with a secondary CCD. Add on L3 V-Cache, and AMD will deliver 224MB of L3 Cache (64MB L3 + 160MB V-Cache). That’s more than double the L3 cache size of today’s Ryzen 9 9800X3D CPUs.
With more cores, more L2 Cache, and larger CCDs, AMD’s Zen 7 CPUs should be impressive offerings. That said, according to Moore’s Law is Dead, AMD could do better.
Could AMD deliver 72 cores on AM5 with “Steamboat”?
AMD is reportedly creating a CPU CCD called “Steamboat” that uses die stacking to put all L3 cache on a secondary die. This means all primary dies can be dedicated to CPU cores. This enables massive space savings at the cost of a larger secondary die, making 3D stacking a requirement. Without die stacking, we would have a CPU die that lacks L3 cache, and that wouldn’t perform well.
AMD’s rumoured “Steamboat” die can reportedly feature up to 36 CPU cores and 252MB of L3 Cache. In theory, AMD could use this die to create Ryzen CPUs, with two of these dies enabling 72-core AM5 CPUs. However, doing this would be incredibly expensive, so much so that this is unlikely to happen with Zen 7.
AMD’s “Steamboat” CPU design is reportedly for EPYC Florence CPUs, which will use eight of these dies to create huge 288-core processors. This CPU would feature 2,016MB of L3 cache.
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