AMD Zen 7 Details Leak – “Grimlock” to use TSMC A14 node
AMD has big plans for Zen 7 – More cores, more cache, and TSMC A14 silicon
AMD is reportedly planning to use TSMC’s A14 lithography node for its Zen 7 “Grimlock” desktop CPUs. The Taiwan Commercial Times has reported that AMD is already preparing its supply chain for Zen 7, with plans to continue to use TSMC’s leading-edge lithography technologies.
AMD is currently ramping up its production of 2nm (N2) Zen 6 CPUs. With Zen 7, AMD will be skipping nodes like N2P, N2X, and A16 (1.6nm) and going straight to A14 (1.4nm). With this node, Zen 7 trial production is expected in 2027, and mass production is expected in 2028.
AMD has begun its supply chain preparations for its next-generation Zen 7 platform ahead of schedule. Supply chain sources reveal that the Zen 7 core chipset (CCD), codenamed Grimlock, will utilise TSMC’s A14 process and incorporate next-generation 3D V-Cache technology.
More cores and more cache
The Taiwan Commercial Times, citing insider speculation, claims that AMD’s Zen 7 flagship will feature CCDs with sixteen CPU cores. With L3 V-Cache, these CCDs will reportedly have a total of 224 MB of L3 cache. That’s 133% more L3 cache than today’s Ryzen 9000 X3D gaming CPU CCDs.
These details are the same as the leaks we reported on last month, which also stated that AMD planned to double its per-core L2 cache with Zen 7. This gives each core 2 MB of L2 cache instead of 1 MB. These enlarged caches will accelerate latency-sensitive workloads, with AMD’s enlarged L3 caches allowing more workloads to fit inside AMD’s X3D V-Cache.
In addition, AMD will also adopt Powertech’s FOPLP (Fan-Out Panel-Level Packaging) in the Zen 7 platform. It is understood that Lisa Su personally visited Powertech during her visit to Taiwan; semiconductor industry insiders speculate that the Zen 7 flagship CCD adopts a 16-core design, and with 3D V-Cache, the L3 cache capacity of a single CCD can reach up to 224MB, which means that more memory must be packed into a larger package size.
According to Moore’s Law is Dead, citing industry sources, AMD is aiming for 15-25% IPC (Instructions Per Cycle) gains with Zen 7. That means more performance per clock cycle. Additionally, AMD plans to deliver new ISA improvements to accelerate AI and optimise interactions between its CPUs and AI accelerators. AMD has already revealed some of this with its Zen CPU roadmap, which confirmed that Zen 6 would feature a “New Matrix Engine” and “AI Data Format Expansion”. While these changes will likely have a small impact within the consumer space, they will have huge implications for AI datacenters. This is especially true of “agentic AI” which, proves to be a large market for AMD.
With Zen 7, AMD is not resting on its laurels. AMD’s moving to a new lithography node, adding more cores, and delivering enlarged L2 and L3 caches. Alongside traditional architectural improvements, these changes should enable greatly increased single-threaded and multi-threaded performance in certain workloads. That’s good news for PC users and great news for AMD. After all, faster processors sell!
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