TSMC to bring back SRAM scaling with its A14 node
TSMC’s upcoming A14 node reportedly comes with a 20% SRAM scaling improvement over N2
TSMC’s recent lithography nodes have suffered from a major scaling issue. SRAM scaling has stagnated for years, with 5nm, 3nm, and 2nm all having a bit cell size of around 0.021 µm². Now, according to a report from ETNews, TSMC plans to resume SRAM scaling with its upcoming A14 node, which is great news for cache-heavy chips.
With A14, TSMC will reportedly bring SRAM cell sizes down to less than 0.017 µm². That’s more than 20% smaller than the SRAM sizes of prior nodes. This should put TSMC ahead of Samsung and Intel, who are unlikely to announce smaller SRAM cell sizes with their competing 14 Angstrom technologies. TSMC will reportedly officially unveil this advancement later this year.
(TSMC SRAM density chart – via ETNews)
Why SRAM scaling matters
While logic transistors have continued to shrink, SRAM scaling has stalled. This means that caches have become much larger relative to other parts of new CPUs and GPUs. This shift has made large caches more expensive and made it harder for chipmakers to produce CPUs and GPUs with larger caches. AMD has worked around this issue by using 3D die stacking to boost the cache sizes of its X3D gaming CPUs.
If A14 delivers real SRAM scaling, chipmakers could make their chips cheaper by shrinking the physical sizes of their caches, or use the freed-up area to give more cache to future chips.
According to TSMC, their A14 node targets a 10-15% speed improvement over N2 at the same power levels or a 25-30% power reduction at the same performance levels. A14 also targets a chip density increase of around 20%.
As memory performance and bandwidth become increasingly severe bottlenecks for modern chips, advances in SRAM scaling could let chipmakers counter this with larger on-chip caches. This could make SRAM scaling a critical feature of TSMC’s A14 node, helping secure the company’s continued leadership in silicon manufacturing.
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