AMD plans to host an EPYC ROME launch event on August 7th

While AMD’s Zen 2 desktop processors are impressive, the company’s plans for the architecture was to win big in the server market. Simply put, AMD’s chiplet design for Zen 2 is purpose-built to tackle the performance downsides of the company’s existing EPYC processors, especially when it comes to memory uniformity and latency.  

During the company’s Q2 2019 earnings call, AMD’s CEO, Lisa Su, confirmed that the company’s 7nm ROME processors would be launched on August 7th at a special event. 

AMD’s EPYC ROME processors are designed to deliver a 2x boost in cores/threads per socket, offering a maximum of 64 cores and 128 threads with EPYC 2. On top of this, AMD also promises a 2x boost in floating-point performance, which when combined with AMD’s core count changed could yield a 4x boost in compute density.  

A=One of the key design improvement for AMD’s EPYC processors is the utilisation of a 14nm I/O chiplet to deliver octo-channel memory access through a singular location, unifying memory access for each of ROME’s Zen 2 chiplets. This is hugely different from Zen 1 EPYC, where each of AMD’s EPYC CPU clusters offered access to two memory channels. This required memory information to be shared between CPU dies, resulting in uneven latencies, an issue that’s addressed with ROME.