Intel discusses the difficulties of increasing CPU frequencies – Why have we not reached 10GHz?

Intel describes CPUs as a conveyor belt, where instructions are designed to be completed in a single clock cycle. Stage 1 happens before stage 2, stage 2 occurs before stage 3, etc. After the first device is finished, it can move to be used by a different instruction, allowing several instructions to be completed simultaneously. In this diagram, things appear very simple, with the maximum clock rate correlating to the speed of the slowest instruction. 

Clock speeds can continue to be increased as long as the slowest instruction can still fit within a single clock window, but what happens when clocks are raised further. 

                     

 

In the diagram below you can see that each stage takes different lengths of time, with stage 3 being the bottleneck. If we try to increase clock speeds further, stage 3 will start taking up two clock cycles, causing problems for any instructions that are set to be completed simultaneously. 

The problem here is that while specific actions will happen at a faster rate, ultimately the system will be bottlenecked by its slowest stage, creating a product that doesn’t get any faster with higher clock speeds. 

There are two ways to solve this design problem. First, there is process node advancement, where reducing the size of the manufacturing node will shrink the size of a processors execution units. In smaller units, electrical impulses have shorter distances to travel and can, therefore, take less time to complete allowing all stages to be increased in speed by a similar amount of time. The longest stage will still be a limiting factor, but at least the stage is shorter than it was before. 

Process node technology is highly sophisticated, with many other factors coming into play that can prevent traditional clock speed increased. This complexity is why we don’t see insane increases in clock speeds when moving to a new process node these days, though that doesn’t mean that new process nodes don’t help. 

  
  
  

The other way to increase clock speeds is to split the longest stage into two processes that can be separated into two clock cycles. While this has been an incredibly successful process in the past, but this becomes a lot more complex after all of the more obvious changes have already been made. 

After a certain point, the longest stage is not much larger than the next largest, offering diminishing returns and the need to redesign huge sections of a processor to deliver a meaningful impact on clock speeds. Compound this with how interconnected a modern processor is, making it extremely challenging to make these kinds of adjustments without substantial architectural overhauls. One stage will affect the next, requiring more complex design changes as processors continue to develop. 

Summary

In the early days of the CPU market, there was a lot of low hanging fruit to gather when it came to processing technology and more obvious processor design changes to make. Today we have a very different story, as all of this fruit has been gathered, and now engineers have to take increasingly challenging steps forward to make a major impact. 

With the development of process technology slowing down increases in performance are becoming increasingly dependant on the engineering talent at companies like AMD, Nvidia and Intel, where increasingly radical design changes are required to increase product performance.  

This is then when we come to the idea of IPC (Instructions Per Clock), where some design changes are made that will increase the productivity of specific areas of processors that sometimes sacrifices clock speeds, explaining why certain CPU generations like Ivy Bridge offered decreased max overclocks but offered improved performance at lower clock speeds. 

For a more detailed summary, we would advise reading Intel’s write-up here. 

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