Leaker hints at HUGE core count boost for AMD’s Zen 6 “Medusa” CPUs
AMD’s Zen 6 “Medusa Ridge” CPUs will reportedly feature 12-core CCDs
According to a leak from Moore’s Law is Dead, AMD’s next-generation Zen 6 “Medusa Ridge” CPUs may use 12-core CCDs. This implies that AMD is aiming to deliver a HUGE increase in CPU core count with their next-generation Ryzen processors. With 50% more CPU cores per CCD, AMD’s next-gen Ryzen 9 CPUs may feature 24 total cores, assuming AMD sticks to their standard dual-CCD Ryzen 9 design scheme.
These new 12-core Zen 6 CCDs will reportedly be used across AMD’s next-generation CPU lineup. They will reportedly be used in AMD’s next-generation EPYC (Venice) CPUs, as well as their Medusa Point/Medusa Halo mobile CPUs. This allows AMD to reuse their Zen 6 CCD design across a broader range of CPUs, increasing their production volumes while lowering overall chip design costs.
AMD will reportedly use TSMC’s 3nm lithography node to create these 12-core Zen 6 CPU CCDs. Currently, it is unknown how much cache these CCDs will contain. If AMD continues to deliver 4MB of L3 cache per core, AMD’s new 12-core CCDs will feature 48MB of L3 cache (without V-Cache), which would be a 50% increase over AMD’s 8-core Zen 5 CCDs. However, this boosted cache size is merely speculation, as AMD could move in a different direction with their Zen 6 CPUs.
As prior leaks have suggested, AMD’s Zen 6 CPUs will use a new interconnect between their CPU CCDs and IO dies. Moore’s Law is Dead’s source states that AMD will use a silicon interposer, which enables a higher bandwidth/lower latency interconnect for users. This should lower memory latencies, increase inter-CCD bandwidth, and help AMD boost Zen 6’s CPU performance.
With 12-core CCDs, we can expect AMD’s next-gen Ryzen CPUs to feature higher core counts. This will boost AMD’s multi-threaded performance significantly. New interconnects should also help to boost the performance of AMD’s dual-CCD chips. Lower latencies and boosted inter-chip bandwidth will alleviate performance issues that multi-CCD AMD CPUs have in some workloads.
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