Reviewers spot major regression in AMD’s high-end Ryzen 9000 series Zen 5 CPUs

Multiple reviewers spot huge inter-CCX latency increase for AMD’s Ryzen 9000 Zen 5 CPUs – Bad news for gamers

We released our review for AMD’s new Ryzen 9 9900X and 9950X CPUs yesterday, and our opinions are mixed. Yes, AMD has delivered strong generational performance increased in many workloads, but there are many areas with minor or no improvement. We also found many instances when AMD’s 12-core and 16-core chips performed significantly worse than their 6-core and 8-core counterparts in games. This was especially true in our Total War Warhammer III test.

Typically, when we see issues like this, inter-chiplet communication is usually the issue. After all, only AMD’s 12-core and 16-core Ryzen 9000 chips feature two CPU CCX (Core Complex) chiplets, making them susceptible to performance issues when inter-chiplet latencies are high. For AMD’s Zen 5 CPUs, we found that performance regressions in workloads that could be slowed down by inter-CCX communications had larger than normal performance regressions with Zen 5.

A major inter-CCX latency regression for Zen 5

Now, several outlets have confirmed that inter-CCX latencies are slower with AMD’s Zen 5 CPUs. Chips and Cheese have reported a 2.5x increase inter-CCX CPU core communication speeds. That’s a major regression for AMD’s Zen 5 CPUs. Currently, it remains to be seen if tis issue can be fixed or mitigated with firmware or software updates.

Zen 5 continues to enjoy very fast cache to cache transfers within a cluster. However, cross-cluster latencies are high compared to prior generations. At nearly 200 ns, cross-cluster latencies aren’t far off from cross-socket latencies on a server platform. It’s a regression compared to prior Zen generations, where cross-cluster latencies were more comparable to worst-case latencies on a monolithic mesh based design.

The Ryzen 9 7950X3D for example typically completes cross-cluster cache transfers in less than 80 ns.

(AMD Ryzen 9 9950X Core-to-Core latency chart – From Chips and Cheese)

What AMD needs to do with Zen 6 and beyond

Simply put, AMD needs to address this chiplet-to-chiplet latency issue with future iterations of Zen. Reduced inter-chip latencies have major benefits for AMD. This includes decreased DRAM latencies, and faster core-to-core communication times. Beyond that, a new chiplet inter-connect technology may also boost chip-to-chip bandwidth, which is another avenue for potential performance improvements.

Today’s Zen CPUs use organic substrates for chip-to-chip communications. This has been the case since AMD launched their first EPYC processors. With Zen 2, inter-chip communications were improved significantly with the introduction of an IO die and dedicated CCX (Core Complex) chiplets. That said, this technology has been used by AMD since Zen 2 launched in 2019. Now it’s time for AMD to move to more advanced chiplet technologies and fight for increased bandwidth, lowered latencies, and heightened communications efficiency.

Thankfully, there are rumours that Zen 6 will be moving to a new chiplet architecture. This would give AMD’s Zen 6 CPUs a similar chiplet design to AMD’s high-end RX 7000 series GPUs. This could allow AMD’s large chiplet-based CPUs to act more like traditional monolithic CPU designs, enabling higher levels of performance. This will be especially true for AMD’s high-end CPU models.

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