PCI-SIG officially releases the PCIe 4.0 standard

This standard is an important development for PCI, offering 2x the bandwidth of PCIe 3.0 per lane, allowing PCIe 4.0 devices to use half the PCIe lanes and offer the same bandwidth as today’s devices or offer two times the connectivity speeds using the same number of lanes. PCIe 4.0 is also designed with several other features in mind, which include reduced system latency and lane margining.

– Extended tags and credits for service devices
– Reduced system latency
– Lane margining
– Superior RAS capabilities
– Scalability for added lanes and bandwidth
– Improved I/O virtualization and platform integration

Version 0.9 of the PCIe 4.0 standard was already feature complete, with this version receiving wide levels of adoption before the PCIe 4.0’s official publication, which means that vendors are already working on implementing PCIe 4.0 into their future devices. 

we’ve seen unprecedented early adoption! Prior to publication, we’ve had numerous vendors confirmed with 16GT/s PHYs in silicon and IP vendors already offering 16GT/s controller. Given the interest, we held a pre-publication Compliance Workshop with preliminary FYI Testing Only for PCIe 4.0 architecture that attracted dozens of solutions. We’re continuing to conduct FYI testing in our workshops throughout the remainder of the year.

 

PCI-SIG has plans to accelerating the development of their future standards, with plans to finalise PCIe 5.0 in Q2 2019, focusing primarily on pure speed increased rather than other feature updates. PCIe 4.0 will offer 2x the bandwidth of PCIe 3.0 while PCIe 5.0 will offer 4x the bandwidth. Version 0.3 of the PCIe 5.0 standard is already available 

Some IP vendors are so eager to adopt PCIe 4.0 that controllers for the standard already exist, albeit using version 0.9 of the standard. 

     

  

While PCIe 3.0 remains more than adequate for the needs of consumers today, this will likely change in the future as NVMe SSDs, Optane system accelerators or more bandwidth hungry GPUs come to market. At a minimum, it will allow consumers to do what they do today with less memory bandwidth, as PCIe 5.0 4x lanes will offer the same bandwidth as a full PCIe 3.0 16x lane configuration.   

  

You can join the discussion on PCIe 4.0’s official publication on the OC3D Forums. 

This standard is an important development for PCI, offering 2x the bandwidth of PCIe 3.0 per lane, allowing PCIe 4.0 devices to use half the PCIe lanes and offer the same bandwidth as today’s devices or offer two times the connectivity speeds using the same number of lanes. PCIe 4.0 is also designed with several other features in mind, which include reduced system latency and lane margining.

– Extended tags and credits for service devices
– Reduced system latency
– Lane margining
– Superior RAS capabilities
– Scalability for added lanes and bandwidth
– Improved I/O virtualization and platform integration

Version 0.9 of the PCIe 4.0 standard was already feature complete, with this version receiving wide levels of adoption before the PCIe 4.0’s official publication, which means that vendors are already working on implementing PCIe 4.0 into their future devices. 

we’ve seen unprecedented early adoption! Prior to publication, we’ve had numerous vendors confirmed with 16GT/s PHYs in silicon and IP vendors already offering 16GT/s controller. Given the interest, we held a pre-publication Compliance Workshop with preliminary FYI Testing Only for PCIe 4.0 architecture that attracted dozens of solutions. We’re continuing to conduct FYI testing in our workshops throughout the remainder of the year.

 

PCI-SIG has plans to accelerating the development of their future standards, with plans to finalise PCIe 5.0 in Q2 2019, focusing primarily on pure speed increased rather than other feature updates. PCIe 4.0 will offer 2x the bandwidth of PCIe 3.0 while PCIe 5.0 will offer 4x the bandwidth. Version 0.3 of the PCIe 5.0 standard is already available 

Some IP vendors are so eager to adopt PCIe 4.0 that controllers for the standard already exist, albeit using version 0.9 of the standard. 

     

  

While PCIe 3.0 remains more than adequate for the needs of consumers today, this will likely change in the future as NVMe SSDs, Optane system accelerators or more bandwidth hungry GPUs come to market. At a minimum, it will allow consumers to do what they do today with less memory bandwidth, as PCIe 5.0 4x lanes will offer the same bandwidth as a full PCIe 3.0 16x lane configuration.   

  

You can join the discussion on PCIe 4.0’s official publication on the OC3D Forums.