AMD to deliver “latency revolution” with Zen 6 Ryzen interconnect tech
AMD’s “bridge die” tech could be revolutionary for Zen 6
AMD aims to deliver a “latency revolution” with Zen 6, at least according to the leaker “Moore’s Law is Dead”. With a “fundamentally better memory controller” and “bridge die” technology, AMD aims to greatly lower memory latencies and boost inter-CCD communication speeds. This addresses the largest shortcomings of AMD’s Zen 5 CPU architecture, which uses the same memory controller and die connection structure as Zen 4.
Another upgrade that Zen 6 delivers is larger CPU CCDs. AMD’s Zen 6 Ryzen CCDs (Core Complex Dies) feature 12 CPU cores, up from 8 cores with Zen 5. With these extra cores comes more L3 cache, allowing more data to be stored inside each CCD. Furthermore, it means that a 12-core Zen 6 CPU will not have to use die interconnects to communicate, unlike 12-core Zen 5 CPUs.
Why Latency is king for Zen 6
To put it simply, latency is the waiting time. Time spent waiting is time where something isn’t being done. By reducing these wait times, CPUs can respond more quickly to changing workloads and complete tasks faster. Even if overall computational performance doesn’t change, lowered CPU latencies can still deliver boosted performance.
Imagine that you need to use a hammer. If you don’t own a hammer and are allowed to use your neighbour’s, you first need to travel to your neighbour’s house, get their hammer, and travel back to use it. This is a slow and tedious process. There’s a lot of wasted time between “needing a hammer” and “using a hammer”. So, how do we make this process faster? Simple, own a hammer and have it close by. If it’s in your garage, you don’t need to walk to your neighbour’s house anymore. Put a toolbox inside your house; you don’t need to go into the garage. If you add a hammer loop to your belt, it will be on your person. All that reduces the time between “needing a hammer” and “using a hammer”. That’s latency reduction. With Zen 6, AMD is reducing wait times to make its CPUs snappier.
(Image from Moore’s Law is Dead)
How AMD is reducing latencies with Zen 6
With Zen 6, AMD is reportedly moving to a faster memory controller. This will result in lowered memory latencies due to higher memory speeds. This means Ryzen users will be able to access memory faster, resulting in higher performance. This should also enable higher levels of memory bandwidth, boosting performance in bandwidth-constrained workloads.
Thanks to AMD’s new “bridge die” interconnect, the CPU core CCDs and memory controller are connected via a faster, lower-latency link. This enables higher data bandwidth between chiplets and lower latency. Again, this means less time waiting for data and more time working. This is the biggest change in AMD’s CPU chiplet interconnect design since Zen 2.
For latency-sensitive workloads, like gaming, AMD’s Zen 6 CPU designs should deliver dramatically improved performance. This will be especially true when Zen 6 CPUs are used with fast DDR5 memory.
I think people might be sleeping on Zen 6 for two reasons. Number one, you get a unified 12-core CCD. So, just right off the bat, if any game needs more than eight cores, it probably doesn’t need more than 12. That’s going to be a pretty big boost.
Number two, for the scenarios where you would like to, you do get a boost from dual V-Cache, but it still could be better because there’s still all that latency communicating between the CCDs, there’s going to be bridge dies that are used with Zen 6 to massively lower that latency between CCDs. And so, I mean, I don’t know. We’ll have to see.
I think with Zen 6, we could see some radically better performance in the scenarios you’re talking about, when they have like a fundamentally better memory controller, and bridge dies between them. And what we’re seeing with the 9950 X3D2 is like a very, very small glimpse of what we’re going to see in some of these applications that will be boosted with Zen 6.
There’s more to Zen 6 than reduced latencies
With twelve cores per CCX, AMD’s Zen 6 Ryzen CPUs will be able to have up to 24 CPU cores using two CCX chiplets. This is a 50% increase in core count over AMD’s existing AM5 Ryzen processors. Furthermore, AMD can deliver up to 12 cores on a single CCX AM5 CPU. Today’s 12-core Ryzen CPUs have two CCX chiplets.
AMD is reportedly using TSMC’s 2nm lithography node to create its new Zen 6 CCX chiplets. Today’s Ryzen 9000 series CPUs use TSMC’s 4nm node. This new node offers advantages in performance, density, and power efficiency. This should allow AMD to boost Zen 6’s core frequencies. Add on other architectural enhancements, and AMD’s Zen 6 is likely to outperform its Zen 5 predecessors by significant margins.
If these rumours about Zen 6 are correct, AMD could deliver one of its biggest generational leaps since the release of Zen/Ryzen. That’s great news for AMD and its customers. After all, who doesn’t want a faster CPU?
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