AMD clarifies why Threadripper uses 4 silicon dies

AMD clarifies why Threadripper uses 4 silicon dies

AMD clarifies why Threadripper uses 4 silicon dies

 
Ever since Der8auer delidded his Ryzen Threadripper 1950X, many false rumours have been circulating online regarding Threadripper’s core configuration and the purpose of all of those CPU dies. 
 
Many thought that Threadripper simply used 4 CPU cores from each die, a point that has been long disproven by AMD, while others thought that these were “failed” Ryzen CPU dies that simply remained inactive. This left many to assume that Threadripper was simply “failed EPYC” though, in reality, nothing can be further than the truth, as AMD has now explained. 
 
It is true that AMD’s Threadripper TR4/SP3r2 socket has the same layout as AMD’s EPYC SP3 socket, using the same substrate design and having an identical external aesthetic. Beyond that things become very different, as EPYC uses four active CPU dies whereas Threadripper only has two, which are in a diagonal configuration to allow heat to more evenly dissipate on the CPU’s IHS. 

  
The question that many have been asking is what the purpose of the other two dies are, with the answer simply being structural. These extra dies prevent imbalance and allow for simple cooler mounting without any chance of damaging the CPU. These two extra dies are not active or even contain working transistors, they are blank and as such are not “wasted Ryzen CPU dies”.

 

AMD clarifies why Threadripper uses 4 silicon dies  

To make a long story short, the two extra dies in Threadripper are merely structural inserts, with the active dies being placed in a diagonal configuration in all Threadripper CPUs to give them all the same thermal profiles. Threadripper CPUs are not “failed EPYC” CPUs and they certainly are not made in a wasteful way by AMD.

Many will ask why AMD did not create a new socket for Threadripper instead of a modified SP3 EPYC socket, but that would require a whole new set of coolers in addition to the coolers that are required for SP3/EPYC and a new socket design which AMD may have been unwilling to create.

 

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