Micron’s driving DDR5 adoption with its Tech Enablement Program – A Peek at DDR5
Micron’s driving DDR5 adoption with its Tech Enablement Program – A Peek at DDR5
In partnership with Cadence, Montage, Rambus, Renesas and Synopsys, Micron wants to push DDR4 into obsolescence, enabling next-generation memory bandwidth for the masses by doubling DDR4’s memory bandwidth capabilities. Micron wants to push per-core bandwidth to unseen levels, countering the huge increases in CPU core counts that we have seen in recent years.Â
The Problem – Why we need DDR5
CPUs are getting larger and larger, and as core counts increase, CPU cores are becoming more and more bandwidth constrained. On mainstream CPU platforms, we have moved from having quad-core processors capping off Intel’s Skylake series to having a 10-core model at the top of their latest Comet Lake series. On the Intel side, up to 10 cores need to be fed with two DDR4 memory channels, and on the AMD side, up to sixteen cores need to be fed with two memory channels.
To enable the next-generation of computing, the industry needs faster DRAM. To fully utilise the power of modern CPU platforms, we need tonnes of memory bandwidth, and the design changes seen with DDR5 will address many of the issues facing DDR4.Â
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A doubling of memory bank groups
With DDR5, each memory module will offer two times as many banks, offering users higher levels of memory density, increasing memory capacity, while also boosting communication efficiency.Â
This design change will increase DDR5’s burst lengths to 16, which increases the efficiency of the memory bus and enables higher data rates than DDR4. On top of this, DDR5 offers onboard ECC, bringing increased reliability to all DDR5 memory modules. Before now, ECC was only available on enterprise/workstation-grade DDR4 modules.Â
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Changing how DDR works to boost performance
With DDR4, the memory locks each rank of memory during a refresh, making much of the memory unusable for a limited time. With DDR5, 1 bank of memory can be refreshed per memory group, which means that the other three banks can operate as normal while another is refreshing.Â
In effect, this allows 75% of the memory banks to operate during bank refreshes, delivering users a considerable performance boost. This will help lower DDR5’s effective memory latency in many scenarios and help deliver users more effective memory bandwidth.Â
DDR5 will offer users two independent 40-bit channels per DIMM to enable 2x as many concurrent operations as DDR4. This alteration will help users of DDR5 get peak performance levels from their memory at all times by parallelising this aspect of DDR5. Â
With DDR5, power management moves from motherboards to modules, allowing DDR5 memory DIMMs to have more control over its power states, delivering cleaner power and improved signalling.Â
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DDR5 offers more than just pure bandwidthÂ
DDR5 isn’t just about increasing memory bandwidth, its about getting more effective bandwidth out of every cycle. In Micron’s testing, its DDR5 memory can offer users a 36% increase in bandwidth over DDR4 when both modules are operating at 3200 MT/s. Without a speed increase, DDR5 can offer 36% more performance.Â
When DDR5 hits the market, Micron plans to release DDR5 memory modules which operate at 4800 MT/s, delivering an 87% increase in performance over 3200 MT/s DDR4 modules. That’s huge, especially after considering DDR5’s potential to deliver higher speeds in the future. Micron is already planning to release 6400 MT/s DDR5 modules.Â
Micron wants to push the DRAM market to DDR5 as fast as possible, and that is great news for PC users. DDR5 offers the potential to increase DRAM performance significantly, and that will introduce a lot of exciting options for software developers.Â
You can join the discussion on Micron’s push for DDR5 memory adoption on the OC3D Forums.Â