TSMC Paves the way to 5nm with Full Design Tools – Promises Performance and Density Boosts
TSMC Paves the way to 5nm with Full Design Tools – Promises Performance and Density Boosts
Yes, 7nm is a significant node shift for the industry, seeing product designs which range from high power/performance computing devices and smaller, low-power mobile devices alike, but that doesn’t mean that manufacturers like TSMC and Samsung can sit on their laurels. In the coming years, we will see two innovations grip the lithography landscape, with EUV nodes and advanced 5nm nodes being on the horizon.
TSMC has announced that they have completed the infrastructure design of their upcoming 5nm process node, their second generation EUV process node which promises improved performance and silicon density over 7nm. Now TSMC has been able to certify full-line EDA (Electronic Design Automation) tools that will allow companies to design products that will be based on the upcoming node.
When building an ARM Cortex-A72 core, TSMC has found that 5nm can offer a 1.8x increase in logic density over 7nm and deliver a 15% speed gain. On top of this TSMC boasts “superior SRAM and analog area reduction”, all of which will be big selling points for the node. TSMC’s 5nm process node is already in risk production.
Much like 7nm, TSMC is targetting 5nm at both low-power mobile products and high-performance computing applications, allowing the node to scale well from desktop-grade processors and graphics cards to mobile phones, tablets and a range of other connected devices.
TSMC’s 5nm process is expected to enter Volume production in late 2020.
You can join the discussion on TSMC’s 5nm performance claims and design tools on the OC3D Forums.