Microchip reveals its first PCIe 5.0 and CXL 2.0 Retimers
Microchip reveals its first PCIe 5.0 and CXL 2.0 Retimers
With PCIe 4.0 and newer connectivity standards, retimers are vital for maintaining signal integrity across large motherboards. The more distance you add between chips, the harder it is for them to communicate effectively at high speeds, and with PCIe 5.0, that signal integrity is harder to achieve than ever.Â
With Microchips latest retimers, which will enter mass production in 2021, PCIe 5.0/CXL signals can be retimed with less than 10 nanoseconds of latency. This places Microchip’s retimers well below the latency specifications of the PCIe 5.0 standard, over 80% lower to be more precise.Â
For larger server motherboards and some consumer-grade motherboards, retimers allow high-speed PCI express lanes to be placed far away from the user’s processor. These chips will become increasingly important as the industry starts to move towards PCIe 5.0, especially within the server market, where large motherboards and long PCIe traces are common.Â
Microchip has been collaborating with Intel to create these retimers, ensuring that they will support Intel’s upcoming Sapphire Rapids Xeon Scalable processors when they launch. These processors will support PCIe 5.0 and CXL connectivity, and Microchip’s retimers will ensure that the server industry is ready to create compatible motherboard designs when these processors are ready to launch.Â
These new XpressConnect chips are already being sampled to customers, paving the way towards the next generation of server products.Â
You can join the discussion on Microchip’s PCIe 5.0/CXL 2.0 retimers on the OC3D Forums.Â