AMD Vega GPU architectural upgrades revealed
AMD Vega GPU architectural upgrades revealed
Â
A word chart has been found hidden in AMD’s Ve.ga website, detailing the architectural upgrades that the company has made to their upcoming Vega series GPUs.Â
Â
This word chart contains marketing words/phrases that AMD associate with their Vega architecture, though at this time we do not know what all of it means. Â
Â
From what we can see here, AMD has redesigned their GPUs cache bandwidth and controller and had redesigned their Polaris compute unit. which means that Vega is not just a larger Polaris GPU with HBM memory but a whole new architecture that the AMD has designed for the high-end GPU market.Â
Â
The statement 2x bandwidth per pin is a clear reference to HBM2, which offers double the bandwidth of the HBM used in the R9 Fury X per chip, with the 8x capacity/stack referring to how HBM2 can have up to 8GB capacities per memory chip. Â
Â
HBM1 was able to offer a maximum capacity of 1GB per stack, which limited AMD’s R9 Fury X to a 4GB frame buffer. With HBM2 Vega should not have this issue. Right now it is unclear how many HBM stacks AMD will be using with Vega, with two stacks offering 16GB of VRAM with 512GB/s of memory bandwidth and four stacks offering 32GB of VRAM and 1024GB/s of memory bandwidth. Â
Â
 Â
Â
Without context a lot of the information here is meaningless, as right now we do not know what AMD are referring to when they talk about their 4x gain in power efficiency or their 2x increase in peak throughput per clock.Â
From what we can see here AMD’s Vega architecture is going to be very interesting from a design perspective, though all of these design changes will need to offer AMD some meaningful performance gains if they want to outperform Nvidia’s current offerings.Â
AMD will be announcing their Vega series of GPUs at CES 2017 on January 5th at 2pm GMT, with a live countdown being visible on AMD’s ve.ga website.Â
Â
You can join the discussion on AMD’s Vega GPU architecture on the OC3D Forums.Â
Â