JEDEC is getting ready to finalise the HBM4 memory standard

HBM4 is coming, and it will transform the AI market

JEDEC has confirmed that they are will soon be ready to finalise their HBM4 memory standard. With this standard, JEDEC promises to deliver HBM users more bandwidth, larger memory capacities, and higher levels of efficiency. That’s everything that the AI market needs to push performance to the next level.

To support an easier transition from HBM3, chips can be designed with memory controllers that support both HBM3/4. This will allow chipmakers to launch products with HBM3 memory and then launch upgraded versions with next-generation memory when it becomes available.

One key upgrade to the 4th generation HBM standard is its 24Gb and 32Gb layers and support for 4-high, 8-high, 12-high, and 16-high TSV stacks. That allows 512Gb (64GB) HBM modules to be created. This paves the way towards AI accelerators and other HBM devices with insane levels memory capacity. That’s perfect for users of large data sets. Even so, not all users will require this level of memory cappacity.

(HBM memory is a vital part of today’s high-end AI accelerators)

Currently, HBM memory is commonplace on high-end accelerators for AI and GPU compute. Sadly, no current-gen consumer GPUs utilise HBM memory. For now, GDDR memory is more cost effective. However, those economics could change as chip packaging technologies advance. HBM memory offers users insane levels of bandwidth, and it would be exciting to see that level of performance on consumer-grade products.

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