TSMC plans to start producing 3D SoIC chips in 2021

Moore’s Law as we knew it is dead, leaving the creators if high-performance computing devices in a tricky position. As an industry, we can no longer rely on smaller nodes coming in a timely manner, or for these nodes to deliver the insane power and performance boosts as their predecessors. In short, humanity is battling physics, and at this stage of the game, all of the low hanging fruit is gone, which means that new leading edge nodes will only become more difficult to create as we move forward. 

Chip makers need a new solution which will allow them to pack more transistors into their products without increasing the cost of their products through larger die sizes and lower chip yields. In some areas, this is already being solved through multi-chip designs, such as AMD’s EPYC and Ryzen Threadripper series processors, but these methods come with downsides, especially when it comes to latency. 

TSMC has another approach which will enable increased silicon density, SoIC (Silicon-on-Integrated-Chips). SoIC is a 3D-IC packaging solution which has a release target of 2021, with TSMC stating that they are “working with a few leading customers” on the technology. Using die stacking, TSMC can interconnect several chips in an incredibly small area, which is great news for small form factor devices like notebooks and smartphones.