Intel’s Raja Koduri teases Xe-powered graphics chips

Intel’s Xe graphics architecture is designed to scale from integrated graphics to ultra-high-end data centre environments. We already know that Intel’s Xe graphics are coming to Intel’s upcoming Tiger Lake series of mobile processors, but after that will come something much bigger. 

Raja Koduri, Intel’s chief architect, has released images of Intel Xe accelerator chips, showcasing what appears to be a tiled design which scales from single-chip (top right) to dual-chip (left) and four-chip (bottom left) models. The latter of these designs are referred to as BFP (big ‘fabulous’ package), by Raja in a recent Tweet. 

Intel believes that a multi-chip design approach will give them a considerable advantage within the data centre market; providing them with similar benefits to AMD’s multi-chip design approach to its EPYC series of server processors. That said, these benefits may not be shared with the PC graphics market, as gaming workloads are latency-sensitive, and the most substantial disadvantage of multi-chip designs are added latencies.  

Right now, Intel’s Xe-HP accelerators are currently being tested within Intel’s Folsom labs, and at this time it is unknown when the company plans to release their first Xe-powered datacenter accelerators.