Zen 3 reportedly contains a hefty single-threaded IPC boost and higher clock speeds

AMD’s Zen 3 architecture is due to start shipping to customers in late 2020, bringing with it new architectural improvements and the promise of enhanced performance/efficiency over today’s Zen 2 hardware. 

If the latest leaks from AdoredTV are to be believed, AMD’s targeting Intel’s single-threaded performance advantage. Rumour has it that AMD has achieved a 10-15% single-threaded IPC uplift with Zen 3, alongside increased boost clock speeds. This IPC/clock speed shift means that Zen 3 is due to offer Ryzen and EPYC users a significant boost in overall system performance, which is excellent news for everyone.

What must be said here is that much of AdoredTV’s information isn’t new, as 13% average IPC increases in integer performance have been reported previously. A 10-15% boost and a 13% average aren’t too dissimilar, and Adored’s other information mostly stems from the early Genoa leaks which we reported on in October 2019.     

AMD’s Martin Hilgeman, their Senior Manager of HPC applications, revealed slides at the HPC AI Advisory Council’s 2019 UK Conference which confirmed that AMD has no plans to adopt an SMT4 configuration with Zen 3. Furthermore, AMD’s slides also suggested that each of their Zen chiplets would continue to offer 8 CPU cores. 

While the slide below claims that AMD’s Zen 3/Milan Processor will offer 32 MB of L3 cache, AdoredTV’s sources claim that each Zen 3 chiplet will continue to feature 32MB of L3 Cache. Perhaps AMD’s mention of 32MB of L3 cache is a reference to additional L3 cache on the other Zen 3 chiplets on future EPYC processors.  

Major Cache Alterations 

This isn’t new information, but AMD’s leaked Zen 3 slides have revealed a combined L3 cache for each Zen 3 chiplet. This alteration unifies the L3 caches of each CPU die and makes L3 cache access times more even across a Zen 3 chiplet. 

Larger cache sizes often mean longer cache latencies, and this is true for Zen 3m though AdoredTV’s source claims that these latencies are only “slightly” increased. Regardless, this increase will be mitigated by more even cache access times, allowing information to be more easily shared between CPU cores. 

This alteration could help increase Zen 3’s multi-threaded performance, especially on single die Ryzen series processors. This change could also improve Zen 3’s gaming performance, just like Zen 2’s doubling of L3 cache accomplished over AMD’s older Zen/Zen series chips. 

Based on these slides, Zen 3 will mark another major design change for AMD’s Zen CPU architecture, offering changes what will be hugely beneficial for the processor’s internal cache latencies. While little is known about AMD’s Zen 3 core design, these slides show us that AMD’s next-generation architecture aims to mitigate more of the shortcomings of AMD’s existing designs. These downsides were already largely reduced with Zen 2, but Zen 3 seeks to take things to another level. 

Zen 4 Leaks? 

AdoredTV’s latest leaks also extend to Zen 4, which is rumoured to feature 1MB of L2 Cache per core and support for AVX512 workloads. Further increases to single-threaded and multi-threaded IPC are planned, as performance/efficiency advantages from 5nm manufacturing. 

Future Intel CPU architectures also reportedly offer larger L2 cache sizes, so it makes sense for AMD to be making similar moves. AVX512 support also allows Zen 4 to compete with Intel in more areas of the market, as AVX512 is practically an Intel-only feature within the X86 CPU market.  

Every interaction of Zen aims to take away the perceived disadvantages of existing Ryzen and EPYC processors. Further increases to single-threaded performance and new features like AVX512 will give customers fewer reasons to buy Intel, and that’s ultimately what AMD’s aiming for. 

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